下述代码描述的状态机结构定义了几个状态？ARCHITECTURE behv OF FSM_EXP ISTYPE FSM_ST IS (s0, s1, s2, s3, S4);SIGNAL c_st, next_state: FSM_ST;-BEGINREG: PROCESS (reset,clk) BEGINIF reset='0' THEN c_st<=s0;ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF;END PROCESS REG;COM:PROCESS(c_st, state_inputs) BEGINCASE c_st ISWHEN s0 => comb_outputs<= 5;IF state_inputs="00" THEN next_state<=s0;ELSE next_state<=s1; END IF;WHEN s1 => comb_outputs<= 8;IF state_inputs="01" THEN next_state<=s1;ELSE next_state<=s2; END IF;WHEN s2 => comb_outputs<= 12;IF state_inputs="10" THEN next_state <= s0;ELSE next_state <= s3; END IF;WHEN s3 => comb_outputs <= 14;IF state_inputs="11" THEN next_state <= s3;ELSE next_state<=s4; END IF;WHEN s4 => comb_outputs <= 9; next_state <= s0;WHEN OTHERS => next_state <= s0 ;END case;END PROCESS COM;END behv;
下述代码描述的状态机结构定义了几个状态？
ARCHITECTURE behv OF FSM_EXP IS
TYPE FSM_ST IS (s0, s1, s2, s3, S4);
SIGNAL c_st, next_state: FSM_ST;-
BEGIN
REG: PROCESS (reset,clk) BEGIN
IF reset='0' THEN c_st<=s0;
ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF;
END PROCESS REG;
COM:PROCESS(c_st, state_inputs) BEGIN
CASE c_st IS
WHEN s0 => comb_outputs<= 5;
IF state_inputs="00" THEN next_state<=s0;
ELSE next_state<=s1; END IF;
WHEN s1 => comb_outputs<= 8;
IF state_inputs="01" THEN next_state<=s1;
ELSE next_state<=s2; END IF;
WHEN s2 => comb_outputs<= 12;
IF state_inputs="10" THEN next_state <= s0;
ELSE next_state <= s3; END IF;
WHEN s3 => comb_outputs <= 14;
IF state_inputs="11" THEN next_state <= s3;
ELSE next_state<=s4; END IF;
WHEN s4 => comb_outputs <= 9; next_state <= s0;
WHEN OTHERS => next_state <= s0 ;
END case;
END PROCESS COM;
END behv;